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74LVX4245 8-Bit Dual Supply Translating Transceiver with 3-STATE Outputs
January 1993 Revised July 1999
74LVX4245 8-Bit Dual Supply Translating Transceiver with 3-STATE Outputs
General Description
The LVX4245 is a dual-supply, 8-bit translating transceiver that is designed to interface between a 5V bus and a 3V bus in a mixed 3V/5V supply environment. The Transmit/ Receive (T/R) input determines the direction of data flow. Transmit (active-HIGH) enables data from A Ports to B Ports; Receive (active-LOW) enables data from B Ports to A Ports. The Output Enable input, when HIGH, disables both A and B Ports by placing them in a high impedance condition. The A Port interfaces with the 5V bus; the B Port interfaces with the 3V bus. The LVX4245 is suitable for mixed voltage applications such as laptop computers using 3.3V CPU's and 5V LCD displays.
Features
s Bidirectional interface between 5V and 3V buses s Control inputs compatible with TTL level s 5V data flow at A Port and 3V data flow at B Port s Outputs source/sink 24 mA at 5V bus; 12 mA at 3V bus s Guaranteed simultaneous switching noise level and dynamic threshold performance s Implements patented EMI reduction circuitry s Functionally compatible with the 74 series 245
Ordering Code:
Order Number 74LVX4245WM 74LVX4245QSC 74LVX4245MTC Package Number M24B MQA24 MTC24 Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 24-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names OE T/R A0-A7 Description Output Enable Input Transmit/Receive Input Side A Inputs or 3-STATE Outputs Side B Inputs or 3-STATE Outputs
Connection Diagram
B0-B7
Truth Table
Inputs OE L L H
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial
Outputs T/R L H X Bus B Data to Bus A Bus A Data to Bus B HIGH-Z State
(c) 1999 Fairchild Semiconductor Corporation
DS011540
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74LVX4245
Logic Diagram
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74LVX4245
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCCA, VCCB) DC Input Voltage (VI) @ OE, T/R DC Input/Output Voltage (VI/O ) @ An @Bn DC Input Diode Current (IIN) @ OE, T/R DC Output Diode Current (IOK) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) and Max Current @ ICCA @ ICCB Storage Temperature Range (TSTG) DC Latch-Up Source or Sink Current 300 mA -65C to +150C 50 mA 200 mA 100 mA 50 mA 20 mA 50 mA -0.5V to VCCA + 0.5V -0.5V to VCCB + 0.5V -0.5V to +7.0V -0.5V to VCCA + 0.5V
Recommended Operating Conditions (Note 2)
Supply Voltage VCCA VCCB Input Voltage (VI) @ OE, T/R Input/Output Voltage (VI/O) @ An @ Bn Free Air Operating Temperature (TA) Minimum Input Edge Rate (t/V) VIN from 30% to 70% of VCC VCC @ 3.0V, 4.5V, 5.5V
Note 1: The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation. Note 2: Unused inputs must he held HIGH or LOW. They may not float.
4.5V to 5.5V 2.7V to 3.6V 0V to VCCA 0V to VCCA 0V to VCCB -40C to +85C 8 ns/V
DC Electrical Characteristics
Symbol VIHA Minimum HIGH Level VIHB VILA Input Voltage Parameter An, T/R, OE Bn VCCA (V) 5.5 4.5 5.0 5.0 Maximum LOW Level VILB VOHA VOHB Input Voltage An, T/R, OE Bn 5.5 4.5 5.0 5.0 Minimum HIGH Level Output Voltage 4.5 4.5 4.5 4.5 4.5 VOLA VOLB Maximum LOW Level Output Voltage 4.5 4.5 4.5 4.5 4.5 IIN Maximum Input Leakage Current @ OE, T/R IOZA Maximum 3-STATE Output Leakage @ An IOZB Maximum 3-STATE Output Leakage @ Bn 5.5 3.6 0.5 5.0 A 5.5 3.6 0.5 5.0 A VI = VIL, VIH OE = VCCA VO = VCCA, GND VI = VIL, VIH OE = VCCA VO = VCCB, GND 5.5 3.6 0.1 1.0 A VCCB (V) 3.3 3.3 3.6 2.7 3.3 3.3 2.7 3.6 3.0 3.0 3.0 3.0 2.7 3.0 3.0 3.0 3.0 2.7 4.5 4.25 2.99 2.8 2.5 0.002 0.18 0.002 0.1 0.1 TA +25C Typ 2.0 2.0 2.0 2.0 0.8 0.8 0.8 0.8 4.4 3.86 2.9 2.4 2.4 0.1 0.36 0.1 0.31 0.31 TA = -40C to +85C Guaranteed Limits 2.0 2.0 2.0 2.0 0.8 0.8 0.8 0.8 4.4 3.76 2.9 2.4 2.4 0.1 0.44 0.1 0.4 0.4 V V V V IOUT = -100 A IOH = -24 mA IOUT = -100 A IOH = -12 mA IOL = -8 mA IOUT =100 A IOL = 24 mA IOUT = 100 A IOL = 12 mA IOL = 8 mA VI = VCCA, GND V VOUT 0.1V or VCC -0.1V V VOUT 0.1V or VCC - 0.1V Units Conditions
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74LVX4245
DC Electrical Characteristics
Symbol ICC Parameter Maximum ICCT/Input @ An, T/R, OE Input @ Bn ICCA Quiescent VCCA Supply Current 5.5 5.5 VCCA (V) 5.5
(Continued)
TA +25C Typ 1.0 1.35 TA = -40C to +85C Guaranteed Limits 1.5 mA VI = VCCA - 2.1V VI = VCCB - 0.6V An = VCCA or GND 3.6 8 80 A Bn = VCCB or GND, OE = GND T/R = GND An = VCCA or GND
VCCB (V) 3.6
Units
Conditions
3.6
0.35
0.5
mA
ICCB
Quiescent VCCB Supply Current 5.5 3.6 5 50 A
Bn = VCCB or GND, OE = GND T/R = VCCA
VOLPA VOLPB VOLVA VOLVB VIHDA VIHDB VILDA VILDB
Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum HIGH Level Dynamic Input Voltage Maximum LOW Level Dynamic Input Voltage
5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0
3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3
1.5 0.8 -1.2 -0.8 2.0 2.0 0.8 0.8
V V V V
(Note 4)(Note 5) (Note 4)(Note 5) (Note 4)(Note 6) (Note 4)(Note 6)
Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: Worst case package. Note 5: Max number of outputs defined as (n). Data inputs are driven 0V to VCC level; one output at GND. Note 6: Max number of Data Inputs (n) switching. (n-1) inputs switching 0V to VCC level. Input-under-test switching: VCC level to threshold (VIHD), OV to threshold (VILD), f = 1 MHz.
AC Electrical Characteristics
TA = +25C CL = 50 pF Symbol Parameters VCCA = 5V (Note 7) VCCB = 3.3V (Note 8) Min tPHL tPLH tPHL tPLH tPZL tPZH tPZL tPZH tPHZ tPLZ tPHZ tPLZ tOSHL tOSLH Propagation Delay A to B Propagation Delay B to A Output Enable Time OE to B Output Enable Time OE to A Output Disable Time OE to B Output Disable Time OE to A Output to Output Skew (Note 9) Data to Output
Note 7: Voltage Range 5.0V is 5.0V 0.5V. Note 8: Voltage Range 3.3V is 3.3V 0.3V. Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design.
TA = -40C to +85C TA = -40C to +85C CL = 50 pF VCCA = 5V (Note 7) VCCB = 3.3V (Note 8) Min 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Max 9.0 9.0 9.0 9.0 10.5 10.5 9.5 9.5 10.0 7.0 7.5 7.0 CL = 50 pF VCCA = 5V (Note 7) VCCB = 2.7V Min 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Max 10.0 10.0 10.0 10.0 11.5 11.5 10.0 10.0 10.0 7.5 7.5 7.5 ns ns ns Units
Typ 5.1 5.3 5.4 5.5 6.5 6.7 5.2 5.8 6.0 3.3 3.9 2.9
Max 8.5 8.5 8.5 8.5 10.0 10.0 9.0 9.0 9.5 6.5 7.0 6.5
1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0
ns
ns
ns
1.0
1.5
1.5
1.5
ns
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74LVX4245
Capacitance
Symbol CIN CI/O CPD Parameter Input Capacitance Input/Output Capacitance Power Dissipation Capacitance (Note 10)
Note 10: CPD is measured at 10 MHz
Typ 4.5 15 BA AB 55 40
Units pF pF pF pF
Conditions VCC = Open VCCA = 5.0V VCCB = 3.3V VCCA = 5.0V VCCB = 3.3V
8-Bit Dual Supply Translating Transceiver
The LVX4245 is a dual supply device capable of bidirectional signal translation. This level shifting ability provides an efficient interface between low voltage CPU local bus with memory and a standard bus defined by 5V I/O levels. The device control inputs can be controlled by either the low voltage CPU and core logic or a bus arbitrator with 5V I/O levels. Manufactured on a sub-micron CMOS process, the LVX4245 is ideal for mixed voltage applications such as notebook computers using 3.3V CPU's and 5V peripheral devices.
Power Up Considerations
To insure the system does not experience unnecessary ICC current draw, bus contention, or oscillations during power up, the following guidelines should be adhered to (refer to Table 1): * Power up the control side of the device first. This is the VCCA. * OE should ramp with or ahead of VCCA. This will help guard against bus contention. * The Transmit/Receive control pin (T/R) should ramp with or ahead of VCCA, this will ensure that the A Port data pins are configured as inputs. With VCCA receiving power first, the A I/O Port should be configured as inputs to help guard against bus contention and oscillations. * A side data inputs should be driven to a valid logic level. This will prevent excessive current draw. The above steps will ensure that no bus contention or oscillations, and therefore no excessive current draw occurs during the power up cycling of these devices. These steps will help prevent possible damage to the translator devices and potential damage to other system components.
TABLE 1. Low Voltage Translator Power Up Sequencing Table
Device Type 74LVX4245 VCCA 5V (power up 1st) VCCB 3V (power up 2nd) T/R ramp with VCCA OE ramp with VCCA A Side I/O logic 0V or VCCA B Side I/O outputs Floatable Pin Allowed No
Please reference Application Note AN-5001 for more detailed information on using Fairchild's LVX Low Voltage Dual Supply CMOS Translating Transceivers.
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74LVX4245
Applications: Mixed Mode Dual Supply Interface Solution
LVX4245 is designed to solve 3V/5V interfacing issues when CMOS devices cannot tolerate I/O levels above their applied VCC. If an I/O pin of 3V ICs is driven by 5V ICs, the P-Channel transistor in 3V ICs will conduct causing current flow from I/O bus to the 3V power supply. The resulting high current flow can cause destruction of 3V ICs through latchup effects. To prevent this problem, a current limiting resistor is used typically under direct connection of 3V ICs and 5V ICs, but it causes speed degradation. In a better solution, the LVX4245 configures two different output levels to handle the dual supply interface issues. The "A" port is a dedicated 5V port to interface 5V ICs. The "B" port is a dedicated port to interface 3V ICs. Figure 2 shows how LVX4245 fits into a system with 3V subsystem and 5V subsystem. This device is also configured as an 8-bit 245 transceiver, giving the designer 3-STATE capabilities and the ability to select either bidirectional or unidirectional modes. Since the center 20 pins are also pin compatible to 74 series 245, as shown in Figure 1, the designer could use this device in either a 3V system or a 5V system without any further work to re-layout the board.
FIGURE 1. LVX4245 Pin Arrangement is Compatible to 20-Pin 74 Series 245
FIGURE 2. LVX4245 Fits into a System with 3V Subsystem and 5V Subsystem
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74LVX4245
Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M24B
24-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide Package Number MQA24
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74LVX4245 8-Bit Dual Supply Translating Transceiver with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC24
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 8 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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